Mentor Graphics Tools for Verification
Mentor Graphics, now part of Siemens EDA, provides a comprehensive set of tools for functional verification, design verification, and physical verification of integrated circuits (ICs) and electronic systems.
1. Questa (QuestaSim / Questa Advanced Simulator)
Purpose:
Functional verification of digital designs.
Key Features:
Supports Verilog, SystemVerilog, and VHDL
Advanced SystemVerilog Assertions (SVA)
Coverage-driven verification
Debug and waveform analysis
Used For:
RTL and gate-level simulation
Testbench development
Functional correctness verification
2. Questa Formal
Purpose:
Formal verification without simulation.
Key Features:
Assertion-based verification
Property checking
Automatic bug detection
Works without test vectors
Used For:
Control logic verification
Finding corner-case bugs
Complementing simulation-based verification
3. Veloce Hardware-Assisted Verification System
Purpose:
Accelerated verification for large and complex designs.
Key Features:
Emulation and acceleration
Fast execution of test cases
Supports hardware/software co-verification
Used For:
SoC verification
Running long regression tests
Early software validation
4. ModelSim
Purpose:
Entry-level functional simulation tool.
Key Features:
Verilog, VHDL, and SystemVerilog support
Interactive debugging
Easy to use for beginners and students
Used For:
Academic learning
Small- to medium-scale designs
Basic simulation and debugging
5. Calibre Verification Suite
Purpose:
Physical verification of IC layouts.
Key Features:
Design Rule Checking (DRC)
Layout vs. Schematic (LVS)
Parasitic extraction (PEX)
Industry-standard accuracy
Used For:
Verifying layout correctness
Ensuring manufacturability
Sign-off verification before fabrication
6. SpyGlass (Power, Lint, CDC)
Purpose:
Early-stage design quality verification.
Key Features:
RTL linting
Clock Domain Crossing (CDC) analysis
Power and reset verification
Used For:
Finding coding issues early
Reducing simulation debugging time
Improving design reliability
7. Tessent (DFT Verification)
Purpose:
Design-for-Testability (DFT) verification.
Key Features:
Scan insertion verification
Fault coverage analysis
ATPG validation
Used For:
Ensuring testability of ICs
Manufacturing test verification
8. Questa Coverage and Verification IP (VIP)
Purpose:
Improved verification completeness.
Key Features:
Protocol-specific Verification IP
Functional and code coverage analysis
Industry-standard protocols (AXI, PCIe, USB, etc.)
Used For:
Faster verification closure
Standard interface validation
Summary Table
Tool Verification Type
Questa Functional Simulation
Questa Formal Formal Verification
Veloce Emulation / Acceleration
ModelSim Entry-level Simulation
Calibre Physical Verification
SpyGlass Lint, CDC, Power
Tessent DFT Verification
Conclusion
Mentor Graphics (Siemens EDA) verification tools cover the entire verification flow, from RTL design checking to final physical sign-off. They help improve design quality, reduce errors, and shorten time-to-market.
Learn VLSI Training in Hyderabad
Read More
Using Synopsys Design Compiler
SQL Basics Every Data Analyst Must Know
Python for Data Analytics: Where to Begin
Visit Our Quality Thought Training Institute in Hyderabad
Subscribe by Email
Follow Updates Articles from This Blog via Email
No Comments