🧠 What Is Synthesis?
Synthesis is the process of converting a Register Transfer Level (RTL) description (written in Verilog or VHDL) into a gate-level netlist made up of standard cells from a technology library.
In other words:
RTL (Behavioral) → Gate-Level (Structural)
Design Compiler performs optimization for area, timing, and power based on design constraints.
⚙️ Inputs and Outputs
Inputs:
RTL Code — Verilog or VHDL files.
Constraints File (.sdc) — Defines timing, clocks, I/O delays, etc.
Technology Libraries (.db) — Contains information about available gates and timing/power characteristics.
Link Libraries / Target Libraries — For mapping and linking the design.
Optional: DesignWare libraries for arithmetic or complex logic.
Outputs:
Gate-Level Netlist (.v) — Logic gates connected according to constraints.
Reports — Timing, area, and power reports.
Logs — Synthesis messages and optimization details.
🧩 Major Steps in Synthesis Using Design Compiler
1. Set Up the Environment
Create a working directory and prepare:
RTL files
Constraint files (.sdc)
Library files (.db)
Example directory:
design/
├── rtl/
│ └── top.v
├── libs/
│ ├── stdcell.db
│ ├── io.db
├── constraints/
│ └── top.sdc
└── scripts/
└── synth.tcl
2. Start Design Compiler
Launch the tool from the terminal:
dc_shell -gui
or for batch mode:
dc_shell -f scripts/synth.tcl | tee synth.log
3. Load Libraries
Tell DC which libraries to use:
set_app_var search_path [list ./rtl ./libs]
set_app_var target_library [list stdcell.db]
set_app_var link_library [list "* stdcell.db io.db"]
Target Library → Cells DC can map logic to.
Link Library → All cells used for linking references.
4. Read the RTL Files
read_verilog ./rtl/top.v
If multiple files:
read_verilog [list ./rtl/file1.v ./rtl/file2.v ./rtl/top.v]
Then:
current_design top
5. Elaborate the Design
Elaboration resolves module hierarchies and checks syntax.
elaborate top
link
6. Apply Design Constraints
Define the design environment using an .sdc file or commands:
Example .sdc:
create_clock -period 5 [get_ports clk]
set_input_delay 1 -clock clk [all_inputs]
set_output_delay 1 -clock clk [all_outputs]
set_drive 1 [all_inputs]
set_load 0.1 [all_outputs]
Read into DC:
source ./constraints/top.sdc
7. Compile the Design
Compile performs mapping and optimization.
There are two common methods:
a) Default Compile
compile
b) Incremental (Better Quality)
compile_ultra
You can also add options:
compile_ultra -gate_clock -no_autoungroup
8. Generate Reports
After compilation, generate important reports:
report_timing > reports/timing.rpt
report_area > reports/area.rpt
report_power > reports/power.rpt
report_qor > reports/qor.rpt
These help check:
Timing: Setup/hold violations.
Area: Number of cells and total silicon usage.
Power: Estimated power consumption.
QoR (Quality of Results): Summary of timing and area.
9. Write the Netlist and Constraints
Export the final synthesized design:
write -format verilog -hierarchy -output netlist/top_netlist.v
write_sdc constraints/top_post_synth.sdc
10. Perform LEC (Logical Equivalence Check)
Before moving to the next step, check that the synthesized netlist is logically equivalent to the RTL.
Tool examples:
Synopsys Formality
Cadence Conformal
🧮 Example TCL Script for Synthesis (synth.tcl)
# Design Compiler Synthesis Script
set_app_var search_path [list ./rtl ./libs]
set_app_var target_library [list stdcell.db]
set_app_var link_library [list "* stdcell.db io.db"]
read_verilog ./rtl/top.v
current_design top
link
source ./constraints/top.sdc
compile_ultra
report_timing > reports/timing.rpt
report_area > reports/area.rpt
report_power > reports/power.rpt
report_qor > reports/qor.rpt
write -format verilog -hierarchy -output netlist/top_netlist.v
write_sdc constraints/top_post_synth.sdc
Run it using:
dc_shell -f scripts/synth.tcl | tee synth.log
🧾 Summary
Step Command Description
Load Libraries set_app_var target_library ... Define mapping cells
Read Design read_verilog Load RTL
Elaborate elaborate top Resolve hierarchy
Constraints source top.sdc Define timing, I/O
Compile compile_ultra Optimize & map to gates
Report report_timing, report_area Analyze performance
Write Output write -format verilog Save gate-level netlist
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