🧠 What is VHDL?
VHDL (VHSIC Hardware Description Language) is a programming language used to model and describe digital electronic systems such as FPGAs and ASICs.
It allows you to design, simulate, and implement hardware circuits using code.
🏗️ Basic Structure of a VHDL File
Every VHDL program has three main parts:
Library Declarations
Entity Declaration
Architecture Body
1. Library Declarations
VHDL uses libraries that contain predefined functions, types, and logic operations.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE; — includes the standard IEEE library.
use IEEE.STD_LOGIC_1164.ALL; — allows use of standard logic types like STD_LOGIC and STD_LOGIC_VECTOR.
2. Entity Declaration
The entity defines the interface of your circuit — its inputs and outputs.
entity AND_Gate is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end AND_Gate;
entity — names the design (AND_Gate).
Port — lists input and output signals.
in, out — direction of the signals.
3. Architecture Body
The architecture describes how the circuit works (the behavior or structure).
architecture Behavioral of AND_Gate is
begin
Y <= A and B;
end Behavioral;
architecture Behavioral — defines the design style (Behavioral, Structural, etc.).
begin ... end — contains the executable statements.
Y <= A and B; — defines how output Y depends on inputs A and B.
⚙️ Complete Example
Here’s a complete simple example of a 2-input AND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_Gate is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end AND_Gate;
architecture Behavioral of AND_Gate is
begin
Y <= A and B;
end Behavioral;
🧩 Common Data Types in VHDL
Type Description Example
BIT Simple 0 or 1 '0', '1'
STD_LOGIC Extended logic (0, 1, Z, X, etc.) '1'
STD_LOGIC_VECTOR Array of bits "1010"
INTEGER Integer values 0, 1, 255
BOOLEAN True/False TRUE, FALSE
🕹️ Process Block (for Sequential Logic)
When designing sequential circuits (flip-flops, counters, etc.), use a process block:
process(clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
This describes a D flip-flop that updates Q on the rising edge of clk.
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