⚙️ What is an FSM?
An FSM (Finite State Machine) is a sequential logic circuit that moves between a finite number of states based on inputs and clock cycles.
FSMs are widely used in:
Control units
Protocol handling
Sequence detection
Traffic light controllers
Digital systems with defined steps
🧩 Types of FSMs
Moore Machine – Output depends only on the current state.
Mealy Machine – Output depends on current state and inputs.
🧠FSM Design Steps
Identify states and assign names (and optionally binary codes).
Define inputs and outputs.
Create a state transition diagram or table.
Write Verilog code:
Define state encoding.
Use sequential logic for state transitions.
Use combinational logic for next state and outputs.
🧱 Basic FSM Coding Template
A clean FSM in Verilog typically has three parts:
State register – Stores the current state.
Next-state logic – Determines the next state based on inputs.
Output logic – Generates outputs based on state (and possibly inputs).
💡 Example: Simple 3-State Moore FSM
Let’s build a simple FSM with 3 states:
IDLE
LOAD
EXECUTE
The FSM transitions as follows:
IDLE → LOAD → EXECUTE → IDLE
🧾 Verilog Code
module simple_fsm (
input wire clk,
input wire reset,
output reg [1:0] state_out
);
// Step 1: Define states using parameters or localparams
localparam IDLE = 2'b00;
localparam LOAD = 2'b01;
localparam EXECUTE = 2'b10;
// Step 2: State registers
reg [1:0] current_state, next_state;
// Step 3: Sequential logic for state transition
always @(posedge clk or posedge reset) begin
if (reset)
current_state <= IDLE;
else
current_state <= next_state;
end
// Step 4: Combinational logic for next state
always @(*) begin
case (current_state)
IDLE: next_state = LOAD;
LOAD: next_state = EXECUTE;
EXECUTE: next_state = IDLE;
default: next_state = IDLE;
endcase
end
// Step 5: Output logic (Moore-type: depends on current state only)
always @(*) begin
state_out = current_state;
end
endmodule
🧠Explanation
localparam defines constant state codes.
current_state is updated on every clock edge.
next_state is determined by logic.
reset initializes the FSM to a known state.
always @(*) ensures combinational behavior.
🧰 Mealy FSM Example (Output depends on input)
module mealy_fsm (
input wire clk,
input wire reset,
input wire in,
output reg out
);
typedef enum logic [1:0] {S0, S1} state_t;
state_t current_state, next_state;
// Sequential block
always @(posedge clk or posedge reset) begin
if (reset)
current_state <= S0;
else
current_state <= next_state;
end
// Next state and output logic
always @(*) begin
case (current_state)
S0: begin
if (in) begin
next_state = S1;
out = 1; // Output depends on input and state
end else begin
next_state = S0;
out = 0;
end
end
S1: begin
if (in) begin
next_state = S1;
out = 0;
end else begin
next_state = S0;
out = 1;
end
end
endcase
end
endmodule
🧾 Tips for Writing FSMs in Verilog
✅ Always use non-blocking assignments (<=) in sequential blocks.
✅ Use blocking assignments (=) in combinational blocks.
✅ Clearly separate state transition and output logic.
✅ Include a reset condition to start in a known state.
✅ Use enumerated types (typedef enum) in SystemVerilog for readability.
✅ Simulate your FSM using a testbench to verify transitions.
⚖️ Summary Table
Feature Moore FSM Mealy FSM
Output depends on Current state State + Input
Response speed One clock delay Immediate
Complexity Simpler More complex
Glitch risk Lower Higher
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