VLSI Design Using SkyWater 130nm PDK
Introduction
The SkyWater 130nm Process Design Kit (PDK) is an open-source semiconductor technology released by SkyWater Technology in collaboration with Google. It enables students, researchers, and engineers to design and fabricate integrated circuits (ICs) using a 130nm CMOS technology node. This PDK is widely used for learning, prototyping, and open-source silicon projects.
Key Features of SkyWater 130nm PDK
Open-source and publicly available
Mature and stable 130nm technology
Supports analog, digital, and mixed-signal designs
Compatible with open-source EDA tools
Proven fabrication through MPW (Multi-Project Wafer) shuttles
VLSI Design Flow Using SkyWater 130nm PDK
1. Specification and Design Planning
The process begins with defining:
Functional requirements
Performance targets (speed, power, area)
Technology constraints
Example: Designing a simple processor, ADC, or digital controller.
2. RTL Design
The circuit functionality is described using Hardware Description Languages (HDLs):
Verilog
SystemVerilog
At this stage:
Logic behavior is defined
No physical details are considered
3. Functional Simulation
RTL code is verified using simulation tools such as:
Icarus Verilog
Verilator
This ensures the design behaves correctly before synthesis.
4. Logic Synthesis
The RTL code is converted into a gate-level netlist using:
Yosys (open-source synthesis tool)
The synthesis uses SkyWater standard cell libraries to map logic gates.
5. Floorplanning
Floorplanning defines:
Chip dimensions
Placement of macros and I/O pins
Power distribution strategy
This step impacts performance and routability.
6. Placement and Routing
Using tools like OpenROAD:
Standard cells are placed
Signal routing is completed
Clock trees are synthesized
The result is a complete physical layout.
7. Physical Verification
Design correctness is verified using:
DRC (Design Rule Check)
LVS (Layout vs Schematic)
Tools:
Magic
Netgen
This ensures the layout follows SkyWater design rules and matches the schematic.
8. Timing, Power, and Signal Integrity Analysis
Analysis includes:
Static Timing Analysis (STA)
Power estimation
Signal integrity checks
This confirms the design meets performance goals.
9. GDSII Generation (Tape-out)
After successful verification:
The final layout is exported as a GDSII file
This file is sent for fabrication
10. Fabrication and Testing
The chip is fabricated using SkyWater’s 130nm process.
Post-silicon steps include:
Packaging
Functional testing
Performance validation
Tools Commonly Used
Yosys – Synthesis
OpenROAD – Physical design
Magic – Layout and DRC
Netgen – LVS
OpenLane – Automated RTL-to-GDS flow
Applications
Educational VLSI projects
Research prototypes
Analog and mixed-signal ICs
Open-source silicon development
Conclusion
VLSI design using the SkyWater 130nm PDK provides a complete, real-world IC design experience using open-source tools. It is ideal for learning semiconductor design, building portfolios, and developing low-cost silicon prototypes.
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