🔹 Definition
Floorplanning is the process of organizing the placement of major functional blocks (macros, standard cell regions, and I/O pads) within the chip area to achieve optimal performance, area, and power goals.
🔹 Objectives of Floorplanning
Optimize chip area – Minimize unused or wasted space.
Improve performance – Reduce wire lengths to minimize delay and power.
Ensure routability – Provide enough space for interconnections and routing channels.
Minimize power consumption – Shorter wires reduce dynamic power.
Ensure thermal and noise control – Proper placement helps in heat dissipation and reduces interference.
🔹 Key Steps in Floorplanning
Define chip outline – Determine the size and shape of the chip or core.
Place macros and blocks – Position large modules (like memory, analog IPs, etc.) based on connectivity.
Define power planning – Plan the power grid and ensure power distribution to all blocks.
Place I/O pads and pins – Decide the locations of input/output pads around the chip.
Create placement blockages – Reserve or restrict certain areas to avoid routing congestion.
Check floorplan quality – Verify for area utilization, wirelength, congestion, and timing.
🔹 Types of Floorplans
Manual floorplanning – Done by designers for small or critical blocks.
Automatic floorplanning – Performed by EDA tools using optimization algorithms.
🔹 Output of Floorplanning
Floorplan file (DEF or LEF/DEF format)
Block and pin locations
Power/ground network plan
Information for placement and routing tools
🔹 Analogy
Think of floorplanning as designing the layout of a building — you decide where each room (block) goes, where doors and corridors (connections) will be, and how utilities (power and water, i.e., power and signals) are distributed.
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