⚡ 1. Power Planning
🔹 Definition
Power planning is the process of designing a power distribution network (PDN) to ensure that every part of the chip receives a stable and sufficient power supply without excessive voltage drop (IR drop) or noise.
It is usually done after floorplanning and before placement.
🔹 Objectives
Provide a reliable power supply to all standard cells and macros.
Minimize IR drop (voltage drop due to resistance in power lines).
Reduce electromigration (EM) – metal damage due to high current density.
Support multiple voltage domains if required (e.g., for low-power design).
Ensure proper ground return path for stable operation.
🔹 Key Elements of Power Planning
Power Rings – Metal rings around the core or macros to distribute power (VDD) and ground (VSS).
Power Stripes/Grids – Horizontal and vertical metal lines that connect the power rings to standard cells.
Power Pads – Entry points for power from outside the chip.
Decoupling Capacitors (Decaps) – Used to stabilize voltage and reduce noise.
Multiple Power Domains – Used in low-power designs (e.g., always-on, switchable blocks).
🔹 Challenges
Managing IR drop and EM at smaller technology nodes.
Designing for low power without performance loss.
Handling multiple supply voltages and power gating regions.
⏱️ 2. Clock Tree Synthesis (CTS)
🔹 Definition
Clock Tree Synthesis (CTS) is the process of distributing the clock signal from the clock source (e.g., PLL) to all sequential elements (flip-flops, registers) in a balanced and timing-accurate manner.
It is done after placement and before routing.
🔹 Objectives
Minimize clock skew – The difference in clock arrival times between flip-flops.
Control clock latency – Time taken for the clock to reach from source to sink.
Reduce power consumption of the clock network.
Ensure signal integrity (avoid noise and cross-talk).
🔹 Clock Tree Structures
H-Tree – Symmetrical and balanced for minimal skew.
Clock Mesh – High performance and robustness (used in CPUs).
Spine/Trunk Tree – Used for irregular designs.
Hybrid Trees – Combination of above structures.
🔹 Steps in CTS
Select clock buffers/inverters from the library.
Insert and connect buffers to balance the tree.
Optimize for skew, latency, and power.
Perform CTS checks – Skew, insertion delay, transition time.
Clock Tree Routing – Route clock nets using top metal layers.
🔹 Challenges
Maintaining low skew in large designs.
Reducing dynamic power (clock network consumes ~30–50% of total power).
Handling clock gating for power reduction.
Avoiding electromagnetic interference (EMI).
🔹 Comparison Table
Aspect Power Planning Clock Tree Synthesis
Purpose Distribute power (VDD, VSS) Distribute clock signal
Stage After floorplanning After placement
Objective Minimize IR drop, EM Minimize skew, latency
Key Components Rings, straps, grids, pads Buffers, inverters, tree structures
Tools Used Power grid analysis tools CTS tools in PnR software
Affects Power integrity Timing and synchronization
Learn VLSI Training in Hyderabad
Read More
What is Floorplanning in VLSI?
Synthesis using Design Compiler
Visit Our Quality Thought Training Institute in Hyderabad
Subscribe by Email
Follow Updates Articles from This Blog via Email
No Comments