🧾 1. DRC (Design Rule Check)
🔹 Definition
Design Rule Check (DRC) is a process that verifies whether the physical layout of the chip follows all the manufacturing design rules set by the semiconductor foundry (e.g., TSMC, Intel, GlobalFoundries).
These design rules ensure that the chip can be fabricated reliably without defects or yield issues.
🔹 Why DRC is Important
To ensure the layout can be manufactured correctly.
To prevent short circuits, open circuits, or patterning errors.
To maintain yield and reliability in production.
🔹 Common DRC Checks
Width Rule – Minimum metal or poly width allowed.
Spacing Rule – Minimum spacing between wires or layers.
Enclosure Rule – How much one layer (like metal) must cover another (like via).
Overlap Rule – Ensure correct overlapping of connected layers.
Antenna Rule – Prevent charge build-up during fabrication.
Density Rule – Maintain uniform metal density for planarization.
🔹 Example
If the foundry requires a minimum metal spacing of 0.14 µm, and your layout has two metal wires 0.12 µm apart → DRC violation!
🔹 DRC Tools
Mentor Graphics Calibre
Synopsys IC Validator (ICV)
Cadence Pegasus
🔍 2. LVS (Layout Versus Schematic)
🔹 Definition
Layout Versus Schematic (LVS) is a verification process that compares the extracted netlist from the physical layout to the original schematic (logical netlist).
It ensures that the layout electrically matches the intended circuit design — i.e., what you built physically is what you designed logically.
🔹 Why LVS is Important
To verify connectivity correctness (no missing or extra connections).
To ensure functionality of the fabricated chip matches the design.
To catch human or tool errors during layout creation.
🔹 What LVS Checks
Device Matching – Each transistor, resistor, or capacitor in the schematic must exist in the layout.
Net Connectivity – All signal connections match between schematic and layout.
Pin Names and Hierarchy – Check that all input/output pins are correctly connected.
Shorts and Opens – Detects missing connections or unintended shorts.
🔹 Example
If your schematic connects transistor M1’s drain to net “OUT,”
but in the layout, the drain connects to net “VDD” → LVS mismatch!
🔹 LVS Tools
Mentor Graphics Calibre LVS
Synopsys ICV LVS
Cadence PVS (Physical Verification System)
🧠 Comparison Table
Feature DRC LVS
Full Form Design Rule Check Layout Versus Schematic
Purpose Check manufacturability Check functional/electrical correctness
Checks Geometry, spacing, widths, density Device connectivity and netlist matching
Ensures Layout follows foundry rules Layout matches schematic
Run Stage After routing (before tape-out) After layout extraction
Violation Example Metal width too small Wrong net connected to transistor
Outcome DRC-clean layout LVS-clean layout
🔹 Analogy
DRC → Like checking if a building’s dimensions and materials meet construction safety codes.
LVS → Like verifying that the electrical wiring in the building matches the architect’s circuit diagram.
✅ In short:
DRC ensures the layout can be built.
LVS ensures it will work as designed.
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